Computer processors may employ error correction hardware to correct errors of various corruption length and properties. Some error conditions exceed the ability of an error correction scheme to correct. In another example, data may become lost or otherwise unavailable for further processing. It is the error processing capabilities and architecture of a computer processor that determines when and how to handle uncorrectable errors, unavailable data errors, and other hardware-based errors within and between functional elements of the computer processor. The error processing architecture is an infrastructure distributed among each of the functional blocks of the computer processor with varying error detection and processing capabilities.
In one example, an error processing architecture may employ an asynchronous message channel path for uncorrected error signaling. The corrupt data is used by the requesting execution unit(s) with the expectation that an error message is delivered early enough to prevent any corruption of the architectural state and subsequent functional elements due to receiving corrupted data. However, since the error message is delivered asynchronously, there is a time-window where thread(s) may continue to execute instructions, which may lead to potential data corruption. The time-window may be small, but it is not zero.